PCI Express is the next generation of PCI (Peripheral Component Interconnect), which is a standard interconnection system that enables the transfer of data between a host device 112 and an attached application layer device 114 of a data transfer system 100, FIG. 1. The PCI Express protocol is implemented using PCI Express core 116. PCI Express core 116 is a hardware controller used to identify and resolve the PCI Express protocol layers: the physical/mac layer 118, the link layer 120 and the transaction layer 122. The data is delivered through an application layer interface 124 to the attached application layer device 114.
PCI Express protocol is a very fast, bandwidth rich protocol, enabling a variety of applications to be implemented through a PCI Express link. Application layer devices 114 can include bandwidth-consuming applications, such as file transfers and multimedia files, latency-sensitive applications, such as real-time video and voice streaming applications, and applications requiring both high bandwidth and low latency, such as video conferencing.
The application layer interface 124 connects the PCI Express core 116 to the application layer device 114. The application layer device 114 may be a single, common address/data bus having a few control signals to insure errorless handshakes between the host 114 and any type of application. For example, the application layer device may be a switch or router connected between the PCI Express core 116 and a number of clients that communicate with the host 112. The application layer device in such a case routes incoming packets to the appropriate client (not shown).
The application layer interface 124 is driven by the transaction layer architecture 122 of the PCI Express core 116. The transaction layer architecture 122 of the PCI Express core 116 typically consists of six FIFO buffers: a non-posted header buffer “NP H” 126, a non-posted data buffer “NP D” 128, a posted header buffer “P H” 130, a posted data buffer “P D” 132, a completion header buffer “C H” 134 and a completion data buffer “C D” 136. The six buffers 126–136 are needed to implement the PCI Express reordering rules for three different types of transfers: 1) posted transfers (typically memory write transfers); 2) non-posted transfers (typically memory read transfers); and 3) completion transfers (also called “read response” transfers). The PCI Express reordering rules are set by the PCI Express Standard and described in the PCI Express Base Specification.